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Section 8.10.1.3: |
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This abstract class defines a state component which is a set of all instantiations of objects of any class sub-typing from this class in addition to the vdm model types used wherever this class name is used. Note that SAME has to be an instantiated class, not an abstract one.
NOTE | See the important note about vdm state in the notes on vdm-sl usage in this specification. |
This abstraction models a generic input/output device which may be of any kind which is, at least potentially, capable of importing and exporting data.
This class defines no features.
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Keith
Hopper. Page last modified: Friday, 17 November 2000. |
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